5. TLB — Translation Lookaside Buffer

The problem: programs use virtual addresses, RAM uses physical addresses. The page table that maps one to the other lives in RAM — so every memory access would need two RAM accesses (page table lookup + actual data). Too slow.

The fix: the TLB is a small, ultra-fast CPU cache of recent virtual→physical translations (64–1024 entries), covering most accesses thanks to locality of reference.

• TLB hit: virtual address → found in TLB → 1 RAM access.
• TLB miss: virtual address → not in TLB → walk the page table in RAM → store the result in TLB → 2+ RAM accesses.

TLB and context switching: Process A and B both use virtual address 0x4021 but it maps to different physical addresses for each. So the OS must flush the TLB on a context switch — Process B starts "cold," and every early access is a miss. This is a major reason context switches are expensive.

ASID optimization: modern CPUs tag each TLB entry with an Address Space ID, so entries from multiple processes can coexist — no full flush needed on switch.

TLB in threads: threads of the same process share the same page table, so TLB entries stay valid across thread switches — another reason thread switches are cheaper.

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